1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method for fabricating a transistor having a fully silicided gate.
2. Description of the Related Art
As semiconductor devices are continuously being miniaturized, the RC delay effect becomes an important issue. To reduce the RC delay effect of a MOS transistor, the gate is usually formed with a metal silicide layer thereon, or is directly formed from a metal that has a lower resistance. The metal gates in a CMOS device are usually formed with a dual-metal process, wherein the gates of NMOS and those of PMOS are formed from two metals with different work functions to achieve symmetric threshold voltages for NMOS and PMOS. In order to simplify the metal gate process, a metal having a work function around silicon's mid-gap value of 4.6-4.7 eV might be used alone to achieve symmetric threshold voltages for NMOS and PMOS. However, such a work function would cause relatively high threshold voltages that do not meet the requirement of high performance in current semiconductor devices.
Recently, CMOS transistors having fully silicided gates for both NMOS and PMOS were reported, wherein the metal silicide material can have two different work functions that contribute to symmetric threshold voltages for NMOS and PMOS. The metal silicide gates are formed with a single full silicidation process of polysilicon gates. The full silicidation process is similar to an ordinary salicide (self-aligned silicide) process, but is continued for a longer period to fully silicide the polysilicon gates. Such a silicide gate is superior to a polysilicon gate for having a lower resistance and no gate depletion effect.
However, since the duration of a full silicidation process is longer and the silicon atoms in the source/drain (S/D) region also react with the metal, the shallow S/D junction of the transistor is easily damaged to cause a junction leakage in the vertical direction. Further, the S/D junction and the channel are easily shorted to cause a leakage in the lateral direction. Such a problem cannot be solved by increasing the depth of the S/D junction, since the depth of the S/D junction must be sufficiently small to prevent the short channel effect (SCE).